The present invention relates to a memory cell (e.g., a static memory) and a memory device, and, more specifically, to semiconductor memory cells with a greater immunity from soft errors caused by alpha rays and a memory device using such memory cells. The present invention is also directed to a method of reducing soft errors in a semiconductor memory cell.
Among conventional measures to prevent soft errors in memory cells is a method of adding capacitance to data storage nodes of static memory cells used in a CMOS or BiCMOS memory. Adding capacitance may be achieved in several ways. But for realizing a memory cell occupying a small area, it is desired that the capacitance to be added be as small as possible and have as large an effect as possible of increasing the stored charge in the memory cell.
In adding capacitance for increasing stored charge, the IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, June 1987, pp. 430-436, states that it is effective to connect capacitance between two data storage nodes of a memory cell.
FIG. 2 is an equivalent circuit of a memory cell employing a conventional measure to prevent soft errors. In FIG. 2, reference number 100 represents a memory cell, which consists of transfer-MOS transistors MN1, MN2, driver-MOS transistors MN3, MN4, load-MOS transistors MP1, MP2, and capacitance C.sub.c added between two data storage nodes (node 1 and node 2, respectively designated by reference characters 102 and 104). FIG. 2 also shows word line 106 and bit line 108. FIG. 3 is an equivalent circuit to describe a memory response to noise current I.alpha. induced by .alpha.-rays of the memory cell of the above construction. By referring to FIGS. 2 and 3, how the soft error immunity of memory cell 100 increases by the conventional method of adding capacitance between the data storage nodes will be described in the following.
In the equivalent circuit of FIG. 3, the node 1 and node 2 are data storage nodes of the memory cell 100 of FIG. 2, and capacitances C.sub.1, C.sub.2 represent capacitance to ground of node 1 and node 2, respectively. These capacitances C.sub.1, C.sub.2 are made up mainly of parasitic capacitance between the diffusion layers and wells of the transistors MN1-MN4, MP1, MP2 or substrate. Capacitance C.sub.3 is a coupling capacitance between node 1 and node 2, and consists of a parasitic capacitance between the diffusion layer and the gate of the transistors MN3, MN4, and the capacitance C.sub.c added between the two nodes.
The pulse width of a noise current I.alpha. induced by .alpha.-rays is generally of the order of 100 ps, which is small compared with a time constant that is determined by the on-resistance of MOS transistor and the capacitance of a data storage node, so that the potential variation of the data storage node can be expressed by an equivalent circuit made up only of capacitances, as shown in FIG. 3. The direction of the noise current I.alpha. differs depending on whether the alpha-rays enter the nMOS transistors MN1-MN4 or pMOS transistors MP1, MP2. In ordinary memory cells, however, because the area occupied by the pMOS transistor is far smaller than that of the nMOS transistor, the amount of noise current I.alpha. induced by the alpha-rays to flow through the pMOS transistor is small. Thus, it is safe to consider that soft errors occur when alpha-rays enter the nMOS transistor and cause the noise current I.alpha. to flow in the direction of the arrow, pulling down the potential of a high-voltage side node. This case of soft error is explained below.
Assuming that the memory cell 100 is in the information holding state, that the potential of the node 1 is at a high level V.sub.H and that the potential of the node 2 is at a low level V.sub.L, a soft error due to irradiation of alpha-rays occurs when the noise current I.alpha. induced by the alpha-rays lowers the potential of the node 1 below that of the node 2. Hence the critical condition for soft error occurrence is given by Equation (1). EQU V.sub.H -V.sub.H =V.sub.L -.DELTA.V.sub.L (Equation ( 1))
Here, .DELTA.V.sub.H and .DELTA.V.sub.L are potential variations of node 1 and node 2, respectively, caused by the noise current I.alpha.. The potential variation at node 1 is capacitance C.sub.3 divided by capacitances C.sub.3 and C.sub.2 and appears at node 2, so that the following relationship of Equation (2) holds between .DELTA.V.sub.H and .DELTA.V.sub.L. ##EQU1##
Substituting Equation (2) into Equation (1) and letting V.sub.H -V.sub.L =V.sub.S (signal amplitude of memory cell) results in Equations (3) and (4). ##EQU2##
If we define a stored charge of memory cell Qm as a minimum charge that must be applied to the node 1 to generate an error in the memory cell 100, then Qm, as expressed by Equation (5), is equal to the product of an equivalent capacitance between node 1 and ground and .DELTA.V.sub.H given by Equation (3). Further, because ordinary memory cells have the relation C.sub.1 =C.sub.2, the Equation (5) can be simplified into Equation (6). ##EQU3##
From Equation (6), it is seen that adding the capacitance C.sub.c between the data storage nodes of the memory cell 10 (i.e., increasing C.sub.3) results in a substantial increase in stored charge, which is two times greater than the stored charge increase obtained by adding a capacitance-to-ground of the same magnitude to the data storage nodes (i.e., increasing C.sub.1 and C.sub.2). Further, the former method need only add a single capacitance to each memory cell, which means that the former has four times as much stored charge increasing capability as the latter method when compared in unit capacitance.
The reason that the conventional method of adding the capacitance C.sub.c between the two data storage nodes--node 1 and node 2--of the memory cell 100 produces a significant stored charge increasing effect is because the added capacitance C.sub.c not only prevents the reduction in potential of the node 1 on the high-voltage side but also reduces the potential of the node 2 on the low-voltage side as the potential of the high-voltage side node 1 decreases, thereby making the reversal of potentials at these nodes unlikely.